Structural Models for Failure Detection of Moore Finite-State Machines

V. V. Solov’ev; Соловьев В. В.

doi:10.31857/S0002338823060100

Structural Models for Failure Detection of Moore Finite-State Machines

Authors: Solov’ev V.V.¹
Affiliations:
1. Bialystok University of Technology, Bialystok, Poland
Issue: No 6 (2023)
Pages: 110-123
Section: DISCRETE SYSTEMS
URL: https://journal-vniispk.ru/0002-3388/article/view/148143
DOI: https://doi.org/10.31857/S0002338823060100
EDN: https://elibrary.ru/GSVCXM
ID: 148143

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Abstract
About the authors
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Abstract

Fault detection is an important task in the design of fault-tolerant state machines. Structural models of Moore finite-state machines are proposed to detect multiple faults in various elements of the finite-state machine and prevent their negative impact on the controlled object. The structural models under consideration make it possible to detect invalid input and output vectors both in each state and for the entire automaton, invalid code of the current and next state of the automaton, and invalid transitions between states. The costs of implementing the proposed structures by area range on average from 3 to 26%, and the speed of the machine either does not change or even increases by an average of 24–30%. Estimates of the area and performance of the proposed structural models of finite-state machines are given, and recommendations for their practical use are given. It is shown that the choice of a suitable structure allows us not to increase the area, and in some cases even leads to an increase in the performance of the finite-state machine.

About the authors

V. V. Solov’ev

Bialystok University of Technology, Bialystok, Poland

Author for correspondence.
Email: valsol@mail.ru
Польша, Белосток

References

Park S., Kim H.T., Lee S., Joo H., Kim H. Survey on Anti-Drone Systems: Components, Designs, and Challenges // IEEE Access. 2021. № 9. P. 42635–42659.
Соловьев В.В. Использование методики ASMD-FSMD при проектировании на программируемых логических интегральных схемах устройств обработки сигналов // РЭ. 2021. Т. 66. № 12. С. 1178–1188.
Salauyou V., Zabrocki Ł. Coding Techniques in Verilog for Finite State Machine Designs in FPGA // Proc. Intern. Conf. on Computer Information Systems and Industrial Management. Belgrade. Serbia: Springer. Cham, 2019. P. 493–505.
Lyons R.E., Vanderkulk W. The Use of Triple-Modular Redundancy to Improve Computer Reliability // IBM J. Research and Development. 1962. V. 6. № 2. P. 200–209.
Aviziens A. Fault-Tolerant Systems // IEEE Transactions on Computers. 1976. V. 100. № 12. P. 1304–1312.
Rochet R., Leveugle R., Saucier G. Analysis and Comparison of Fault Tolerant FSM Architecture Based on SEC Codes // Proc. IEEE Intern. Workshop on Defect and Fault Tolerance in VLSI Systems. Venice. Italy: IEEE, 1993. P. 9–16.
Niranjan S., Frenzel J.F. A Comparison of Fault-Tolerant State Machine Architectures for Space-Borne Electronics // IEEE Transactions on Reliability. 1996. V. 45. № 1. P. 109–113.
Carmichael C. Triple Module Redundancy Design Techniques for Virtex FPGAs // Xilinx Application Note XAPP197.1. 2001.
Pontarelli S., Cardarilli G.C., Malvoni A., Ottavi M., Re M., Salsano A. System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology // Proc. IEEE Intern. Sympos. on Defect and Fault Tolerance in VLSI Systems. San Francisco. USA: IEEE, 2001. P. 455–460.
Lima F., Carro L., Reis R. Designing Fault Tolerant Systems into SRAM-Based FPGAs // Proc. 40th Annual Design Automation Conf. Anaheim. USA: Machinery, 2003. P. 650–655.
Burke G.R., Taft S. Fault Tolerant State Machines. Washington. USA: NASA, 2004.
Berg M.A. Simplified Approach to Fault Tolerant State Machine Design for Single Event Upsets // Mentor Graphics Users’ Group User2User Conf. Santa Clara. USA, 2004.
Tiwari A., Tomko K.A. Enhanced Reliability of Finite-State Machines in FPGA Through Efficient Fault Detection and Correction // IEEE Transactions on Reliability. 2005. V. 54. № 3. P. 459–467.
Cassel M., Lima F. Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs // Proc. 12th IEEE Intern. On-Line Testing Sympos. Lake Como. Italia: IEEE, 2006. P. 139–144.
Frigerio L., Salice F. RAM-Based Fault Tolerant State Machines for FPGAs // Proc. 22nd IEEE Intern. Sympos. on Defect and Fault-Tolerance in VLSI Systems. Rome. Italy: IEEE, 2007. P. 312–320.
Azambuja J.R., Sousa F., Rosa L., Kastensmidt F.L. Evaluating Large Grain TMR and Selective Partial Reconfiguration for Soft Error Mitigation in SRAM-Based FPGAs // Proc. 15th IEEE Intern. On-Line Testing Sympos. Lisbon. Portugal: IEEE, 2009. P. 101–106.
El-Maleh A.H., Al-Qahtani A.S. A Finite State Machine Based Fault Tolerance Technique for Sequential Circuits // Microelectronics Reliability. 2014. V. 54. № 3. P. 654–661.
Sooraj S., Manasy M., Bhakthavatchalu R. Fault Tolerant FSM on FPGA Using SEC-DED Code Algorithm // Proc. Intern. Conf. on Technological Advancements in Power and Energy. Kollam. India: IEEE, 2017. P. 1–6.
Nidhin T.S., Bhattacharyya A., Behera R.P., Jayanthi T., Velusamy K. Verification of Fault Tolerant Techniques in Finite State Machines Using Simulation Based Fault Injection Targeted at FPGAs for SEU Mitigation // Proc. 4th Intern. Conf. on Electronics and Communication Systems. Coimbatore. India: IEEE, 2017. P. 153–157.
Choi S., Park J., Yoo H. Area-Efficient Fault Tolerant Design for Finite State Machines // Proc. Intern. Conf. on Electronics, Information, and Communication. Barcelona. Spain: IEEE, 2020. P. 1–2.
Verducci O., Oliveira D.L., Batista G. Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices // Proc. IEEE 13th Latin America Sympos. on Circuits and System. Santiago. Chile: IEEE, 2022. P. 1–4.
Климович А.С., Соловьев В.В. Структурные модели конечных автоматов при их реализации на программируемых логических интегральных схемах и системах на кристалле // Изв. РАН. ТиСУ. 2015. № 2. С. 68–80.
Yang S. Logic Synthesis and Optimization Benchmarks user Guide. Version 3.0 // Microelectronics Center of North Carolina (MCNC). North Carolina. USA: MCNC, 1991.
Климович А.С., Соловьев В.В. Преобразование автомата типа Мили в автомат типа Мура путем расщепления внутренних состояний // Изв. РАН. ТиСУ. 2010. № 6. С. 70–79.
Соловьев В.В. Синтез быстрых конечных автоматов на программируемых логических интегральных схемах путем расщепления внутренних состояний // Изв. РАН. ТиСУ. 2022. № 3. С. 69–80.