An 8-bit flash analog-to-digital converter with an array of redundant comparators

Abstract

The circuit design and the topology of an 8-bit analog-to-digital converter (ADC) are presented. It is shown that the differential nonlinearity can be reduced by using three comparators and a majorizing element for formation of each bit of the thermometric code. Computer simulation and measurements of reference ADC chips fabricated using the UMC 180-nanometer CMOS technology confirmed the operability of the proposed design. A power consumption of 93 mW, an effective number of bits of 5.8, and a differential nonlinearity of 0.03 bits have been obtained