Design of integrated voltage multipliers using standard CMOS technologies

A. S. Sinyukin; Синюкин А. С.; B. G. Konoplev; Коноплев Б. Г.; A. V. Kovalev; Ковалев А. В.

doi:10.31857/S0544126923600203

Design of integrated voltage multipliers using standard CMOS technologies

Authors: Sinyukin A.S.¹, Konoplev B.G.¹, Kovalev A.V.¹
Affiliations:
1. Design Center for the Microelectronic Component Base for Artificial Intelligence Systems, Southern Federal University
Issue: Vol 52, No 6 (2023)
Pages: 508-517
Section: ПРИБОРЫ
URL: https://journal-vniispk.ru/0544-1269/article/view/231921
DOI: https://doi.org/10.31857/S0544126923600203
EDN: https://elibrary.ru/HPMCNY
ID: 231921

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Abstract
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Abstract

Results of the design of the integrated multistage voltage multipliers as components of supply modules for wireless passive microdevices are presented. Parameters of MOS transistors significant for the multipliers design and presented in three standard CMOS technologies, CM018G 180 nm, HCMOS8D 180 nm and C250G 250 nm, are considered. CAD Cadence simulation results have demonstrated that in the case of eight-stage multiplier implementation using CM018G technology minimum output voltage level requisite for microchip operation is achieved at input amplitude 250 mV and in the case of the similar device implementation using HCMOS8D technology - at 375 mV. Using sixteen-stages multiplier as example it is shown that voltage multiplication efficiency is from 20% to 54% for wide range of the input voltage, and the efficiency decreases only by 1-3% compared to eight-stage implementation. Proposed recommendations for the integrated voltage rectifiers-multipliers design could be applied at development of the passive supply units for microelectronic devices.

Keywords

structural health monitoring, voltage multiplier, standard CMOS technologies, nanoscale MOS transistors, subthreshold operation mode

References

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