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Simulation of Silicon FETs with a Fully Enclosed Gate with a High-k Gate Dielectric
- Authors: Masalskii N.V.1
-
Affiliations:
- Scientific Research Institute for System Analysis, Russian Academy of Sciences
- Issue: Vol 52, No 4 (2023)
- Pages: 256-261
- Section: МОДЕЛИРОВАНИЕ
- URL: https://journal-vniispk.ru/0544-1269/article/view/138555
- DOI: https://doi.org/10.31857/S0544126923700278
- EDN: https://elibrary.ru/UBVMOR
- ID: 138555
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Abstract
The electrical and physical characteristics of a cylindrical silicon field-effect nanotransistor (FET) with a fully enclosed gate with Al2O3 and HfO2 gate oxide dielectrics are discussed. The numerical simulation results show that the use of high k dielectrics has a noticeable effect on all the main characteristics of the tran-sistor compared to silicon oxide. It follows from the data obtained that, when scaling, the degree of degradation of the electrical and physical characteristics of the transistor is correlated with the level of k: it decreases with the growth of k. This is due to the fact that the decrease in the effect of the gate on the characteristics of the transistor structure, especially in the subthreshold region, is partially compensated by the use of dielectrics with a high k.
About the authors
N. V. Masalskii
Scientific Research Institute for System Analysis, Russian Academy of Sciences
Author for correspondence.
Email: volkov@niisi.ras.ru
Moscow, 117218 Russia
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